1. Field of the Invention
The invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device and an arrangement method thereof which can reduce a layout area size.
2. Description of the Related Art
A typical semiconductor memory device includes a memory cell array region and a peripheral circuit region, and data signal lines (e.g., local data IO signal line and global data IO signal line) for receiving and outputting data are arranged on two layers above the regions.
As semiconductor memory devices have become more highly integrated and operating speeds have become faster, the number of data lines have increased, leading to larger layout area sizes.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device and an arrangement method thereof. Reference numeral 10 denotes a memory cell array, reference symbol CJ denotes a conjunction region, reference symbol SWD denotes a sub word line driver region, reference symbol SA denotes a sense amplifier region, and reference symbol SMCA denotes a sub memory cell array region. And reference symbol MC denotes a memory cell, reference symbol BL denotes a bit line, reference symbol PX denotes word selecting signal lines, reference symbol NWL denotes main word lines, reference symbol SWL denotes sub word lines, reference symbol CSL denotes a column selecting signal line, reference symbol LIO denotes a local data input and output line, and reference symbol GIO denotes a global data input and output line. In the memory cell array 10 of FIG. 1, blocks which include a conjunction region CJ, a sub word line driver region SWD, a sense amplifier region SA, and a sub memory cell array region SMCA are repeatedly arranged in transverse and vertical directions. A sub memory cell array is arranged in the sub memory cell array region SMCA, a control signal generating circuit for controlling a sub word line driver and a control signal generating circuit for controlling a sense amplifier are arranged in the conjunction region CJ, sub word line drivers are arranged in the sub word line driver region SWD, and sense amplifiers are arranged in the sense amplifier region SA.
The function of the components and signal line arrangement of the semiconductor memory device of FIG. 1 are explained below.
The sub memory cell array region SMCA includes memory cell MC connected between a sub word line SWL and a bit line BL, and write/read data to/from the selected memory cell MC. The sense amplifier of the sense amplifier region SA amplifies data of the bit line BL. The sub word line driver region SWD combines signals transmitted to a word selecting signal line PX and a main word line NWL to select the sub word line SWL. Even though not shown, the sub word line driver in the sub word line driver region SWD operates in response to a control signal transmitted from the control signal generating circuit of the conjunction region CJ.
The sub word line SWL is arranged in a vertical direction, and the bit line BL is arranged in a transverse direction. The column selecting signal line CSL, arranged in the same direction as the bit line BL, crosses over the sense amplifier region SA and the sub memory cell array region SMCA, while the main word line NWL, arranged in the same direction as the sub word line SWL, crosses over the sub word line driver region SWD and the sub memory cell array region SMCA. The word line selecting signal line PX, arranged in the same direction as the sub word line SWL, crosses over the conjunction region CJ and the sense amplifier region SA.
FIG. 2 is a block diagram illustrating an arrangement method of the semiconductor memory device of FIG. 1. Referring to FIG. 2, blank boxes show first metal layers arranged in the same layer as the second local data IO signal line, and hatched boxes show second metal layers which connect the first metal layer and the second metal layer to each other and are arranged in different layers from the first and third layers. In FIG. 2, reference symbol SA denotes a sense amplifier region, reference symbol LGIOMUX denotes a local global multiplexer region which transmits data between a local data IO signal line LIO and a global data IO signal line GIO, reference symbol SMCA denotes a sub memory cell array region, reference symbol CJ denotes a conjunction region, reference symbol SWD denotes a sub word line driver region, reference symbol C/D denotes a column address decoder, reference symbol IOSA denotes an input and output sense amplifier, and reference symbol PERI denotes a peripheral circuit region including a row address decoder. In addition, reference symbol LIO denotes a local data IO signal line, reference symbol GIO denotes a global data IO signal line, reference symbol DIO denotes a data IO signal line, reference symbols P1 and P2 denote power lines, and reference symbol CON denotes a sub word line driver control signal line.
Referring to FIG. 2, local data IO signal lines LIO are arranged on a first layer in a vertical direction and cross over the sense amplifier region SA and the conjunction region CJ. Global data IO signal lines GIO are arranged on a second layer in a transverse direction and cross over the sense amplifier region SA and the sub memory cell array region SMCA. Global data IO signal lines GIO are also arranged on the first layer in a vertical direction in a space 1 between the sense amplifier region SA and column address decoders C/D. Further, global data IO signal lines GIO are arranged on the second layer in a transverse direction in a space 2 between the column address decoders C/D next to the sub word line driver region SWD so that they may be connected to the IO sense amplifiers IOSA. Data IO signal lines DIO, which are lines of transmitting signals outputted from the IO sense amplifiers IOSA to a peripheral circuit region PERI, are arranged on a region next to the IO sense amplifiers IOSA on the first layer in a vertical direction.
A power line P2 for supplying electrical power to the IO sense amplifiers IOSA is arranged on the first layer in a vertical direction, and a power line P1 for supplying electrical power to the sub word line driver region SWD is arranged on the second layer in a transverse direction. Since the sub word line driver region SWD requires a high voltage, the power line P1 is designed to have a wider width than the other lines.
Even though not shown, the word selecting signal lines PX, the main word lines NWL and the sub word lines SWL are arranged on the first layer in the same direction as the local data IO signal lines LIO, and the column selecting signal lines CSL are arranged on the second layer in the same direction as the global data IO signal lines GIO. Also, in spaces of the first and second layers in which signal lines are not arranged, other power lines are arranged in the same direction as the local data IO signal lines LIO or the global data IO signal lines GIO, respectively.
The above described arrangement method of the conventional semiconductor memory device has the following disadvantages.
First, as the number of local data IO signal lines LIO is increased, a layout area size of the sense amplifier region SA is also increased. The number of the local data IO signal lines LIO is increased according to increases in density and operating speed of the semiconductor memory device. That is, an increase in density of the semiconductor memory device leads to an increase of memory capacity, whereby the number of the local data IO lines per a unit area is also increased. As a typical method of increasing the operating speed of the memory, the semiconductor memory device increases the amount of data outputted simultaneously from the memory cell array and performs a parallel-to-serial conversion the data before outputting the data for the read operation, and performs a reverse procedure for the write operation. If the operating speed of the memory is increased, the local data IO signal lines LIO is also increased in number.
Therefore, as shown in FIG. 2, the local data IO signal lines LIO are arranged on the first layer above the sense amplifier SA. If the number of the local data IO signal lines LIO is increased, then a layout area size of the sense amplifier region SA is also increased. That is, the efficiency of the layout area size of the semiconductor memory device degrades.
Next, as shown in FIG. 2, since the global data IO signal lines GIO are arranged only in a transverse direction above the sense amplifier SA and the sub memory cell array region SMCA, spaces 1 and 2 are needed. Therefore, the spaces 1 and 2 become larger as the number of the global data IO signal lines GIO is increased.
Even though not shown, the column address decoder C/D has a repair circuit, which connects redundant memory cells in case where inferiority occurs in some memory cells. The repair circuit includes fuses, which should be cut to use the redundant memory cells. Thus, signal lines are not arranged above the column address decoder C/D.
Therefore, as shown in FIG. 2, in order to transmit data transmitted to the global data IO signal lines GIO to the peripheral circuit region PERI through the IO sense amplifier IOSA, the global data IO signal lines GIO are arranged in a transverse direction above the sense amplifier region SA and the sub memory cell array region SMCA, in a vertical direction in a space 1 between the sense amplifier region SA and the column address decoder C/D, and in a transverse direction in a space 2 between the column address decoders C/D. Thus, the spaces 1 and 2 are needed in the arrangement method of the conventional semiconductor memory device of FIG. 2. Further, as described above, with the semiconductor memory device having a higher integration and a higher operating speed, the number of the local data IO signal lines LIO is increased and, thus, the number of the global data IO signal lines GIO is increased. As a result, the spaces 1 and 2 become larger, leading to a larger layout area size of the semiconductor memory device. Therefore, there may be a case where it may be impossible to arrange the global data IO signal lines GIO as shown in the arrangement of FIG. 2.
Also, if the global data IO signal lines are arranged as described above, the 10 sense amplifiers IOSA are arranged not in the peripheral circuit region PERI but next to the column address decoders C/D. In such instance, the separate power line P2 is needed to supply the electrical power from the peripheral circuit region PERI, and the data IO signal lines DIO are also needed to transmit signals between the IO sense amplifiers IOSA and the peripheral circuit region PERI. Even though the electrical power is supplied through the power line P2, a voltage drop follows as the IO sense amplifiers IOSA are farther from the peripheral circuit region PERI, leading to various problems.
Finally, since the global data IO signal lines GIO are arranged in a transverse direction above the sense amplifier SA and the sub memory cell array region SMCA, the local global IO multiplexer LGIOMUX, which connects the local data IO signal lines LIO and the global data IO signal lines GIO, should be arranged in the sense amplifier region SA. In such instance, the sense amplifier region SA lacks spaces due to other circuits. Thus, the length of the global data IO signal lines GIO, which extends from the local global IO multiplexer LGIOMUX to the IO sense amplifiers IOSA, becomes lengthy, whereby the layout area is increased.